The present invention is concerned with failure analysis for semiconductor devices, which in more particular relates to a structure and method for failure analysis. For mass production of semiconductor devices, reliable processing technologies capable of offering payable yields are desired. Procedures for improving the reliability and stability of processing technologies include the steps of designing semiconductor devices, manufacturing samples of the semiconductor devices, and testing the samples. Failure analysis of semiconductor devices is a feedback procedure that involves locating and curing the sources of defects so as to overcome the problems that may arise from the defects.
The strategy of designing and fabricating a semiconductor device can be highly intertwined with failure analysis results. Therefore, an appropriate failure analysis is critical in improving semiconductor device qualities. Incorrect failure analysis can lengthen the term required for developing and advancing semiconductor device products. Thus, fast and accurate failure analysis is highly important in reducing the development term in bringing a semiconductor device to market.
In general, semiconductor wafers contain test patterns, which are formed with various design rules, in purpose of effectively analyzing failure substantials. Varieties of electrical measurements carried on the test patterns are utilized to evaluate structural and electrical characteristics of various microscopic architecture forming electronic circuits in semiconductor devices. For this, the test patterns are designed to monitor structural/electrical characteristics of elements constituting semiconductor devices.
A process for manufacturing a semiconductor device may be divided into the front-end process including steps taken prior to transistor formation, and the back-end process including steps following transistor formation. The back-end process includes a step of forming an interconnection structure to connect the transistors with each other, and a step of forming an interlevel insulation film in order to mechanically support and to electrically insulate the interconnection structure. U.S. Patent US2003-034558, to Eiichi Umemura et al., discloses a technique for treating a test pattern with a contact chain structure in order to evaluate the performance of the back-end process. While such a technique is capable of finding interconnection-type defects (i.e., short circuits or open circuits), it is impossible to obtain detailed information about the types and positions of the defects.
When accurate positions of certain defects are known, semiconductor substrates at the defect positions may be precisely cut out by means of a focused ion beam (FIB) and the sections thereof may be enlarged to a dimension that is suitable for inspection by a scanning electron microscope (SEM). However, since no information about the defect positions is available, a large number of wafer-cutting processes are required to obtain optical features with enlarged sections for analysis by inspection. In other words, if defective locations are included in the sections obtained by the wafer-cutting processes, the defects may be enlarged into a dimension capable of being inspected by the SEM. Otherwise, without the availability of any information related to the location of the defective locations, there is no assurance of inclusion with the defective locations in sections obtained by the wafer-cutting processes. As a result, many wafer-cutting processes are required. Specifically, in the case of analyzing semiconductor devices having defects in a restricted number, a test wafer would be damaged to such a degree by wafer cutting operations that failure analysis is rendered impossible. Consequently, development delays can result due to lack of determination of reasons for failure.